As integrated circuits become increasingly complex, the need for increased packaging density, reduced device parasitics, and low resistivity interconnects increases. Silicide local interconnects have been utilized to reduce pitch requirements, device parasitics, and interconnect resistances.
A common technique employed to form silicide interconnects in semiconductor manufacture is the self-aligned silicide (“salicide”) process. The salicide process involves depositing a blanket layer of a refractory metal layer and amorphous silicon on the semiconductor. A masking resist layer is used to pattern the amorphous silicon. The resist is stripped, and an annealing step is then carried out to cause the refractory metal in contact with silicon to form a silicide. Selective etching is then used to remove the unreacted refractory metal. Often additional annealing is required to lower the resistivity of the silicide contacts.
During the resist stripping process, the refractory metal is exposed at regions not covered with the resist pattern. This can lead to the refractory metal becoming oxidized or thinned by plasma. The damaged metal film may inhibit the silicidation reaction and prevent the formation of a silicide of good quality and low resistance. In addition, monocrystalline silicon, such as the semiconductor substrate, is consumed faster than amorphous silicon during the silicidation process. The difference between the silicidation rates may lead to problems within the integrated circuit. Because the metal atoms are prone to rapidly diffuse into a silicon substrate, the metals can reach shallow junctions formed in source/drain regions and cause leakage at the junction.
Accordingly, it may be desirable to overcome the deficiencies and limitations described hereinabove.